1. Field of the Invention
The present invention relates to a semiconductor memory apparatus, and particularly to a static random access memory.
2. Description of Related Art
Because of the high process compatibility of a Static Random Access Memory (hereinafter referred to as an SRAM), SRAMs have been heretofore mounted to various functional blocks such as CPU. Higher integration and higher speed of a semiconductor apparatus have been achieved by miniaturizing transistors, which are basic elements of the semiconductor apparatus. SRAMs mounted to semiconductor apparatuses are also required to be miniaturized.
FIG. 2 illustrates an SRAM of a related art. FIG. 2 illustrates a SRAM memory cell (hereinafter referred to as an SRAM cell) of a related art including 6 transistors. Access transistors N3 and N4 are switched ON/OFF according to a voltage level of a first word line WL. Further, data (memory data) is held by a latch which is composed of 2 CMOS (Complementary Metal Oxide Semiconductor) inverters.
FIG. 10 illustrates the entire structure of an SRAM according to a related art in which the SRAM cells of FIG. 2 are arranged two-dimensionally. In the circuit of FIG. 10, an SRAM cell is accessed by a first word line WL, and a first bit line pair BL0 and BL1. In a read operation, the first word line WL is activated according to a row address signal RA. This turns on the access transistors N3 and N4, which are provided to all the SRAM cells connected to the corresponding first word line WL. That is, a memory node pair (drain terminal side nodes of N3 and N4 in FIG. 2) is connected to the first bit line pair BL0 and BL1 (source terminal side nodes of N3 and N4), which is charged with a power supply voltage VDD, and memory data is output to the first bit line pair BL0 and BL1. Next, the first bit line pair BL0 and BL1 is selected according to a column address signal CA by a bit line pair selector SEL, and then output. A signal output from the bit line pair selector SEL is input to a sense amplifier SA. A potential difference of the signals input to the sense amplifier SA is amplified, and then output as a read signal. For a stable read out operation, sufficient read margin must be ensured in all the SRAM cells selected by the row address signal RA.
For a write operation, the first bit line pair BL0 and BL1 is selected by the bit line pair selector SEL according to the column address signal CA. The selected first bit line pair BL0 and BL1 is connected to a write driver WD. At this time, the write driver WD discharges either the first bit line pair BL0 or BL1 to generate a potential difference between BL0 and BL1. For example, if write data is “1”, the bit line BL1 is discharged to reduce the voltage level. If the write data is “0”, the bit line BL0 is discharged to reduce the voltage level. Next, the first word line WL is activated according to the row address signal RA. Then the data is written to the selected SRAM cell. While the row address signal RA is activated at this time, a pseudo read operation is performed to the SRAM cells not selected by the column address signal CA. For a stable write operation, sufficient write margin must be ensured in the SRAM cell selected by the column address signal CA, and sufficient read margin must also be ensured in the SRAM cell not selected by the column address signal CA.
In recent years, along with the miniaturization of CMOS processes, the increase in the device variation in transistors making up a SRAM cell is becoming prominent. The increase in the device variation causes issues such that memory data can easily be destroyed in a SRAM cell at the time of a read operation, and that a read current decreases thereby reducing a read speed. As a result, problems are generated including a decrease in yield of a large scale semiconductor memory apparatus. Accordingly, in order to ensure a constant yield, SRAM cell size must be increased to reduce the device variation.
The solution against such issues is suggested by Kawasumi, A. et al., in “A Single-Power-Supply 0.7V 1 GHz 45 nm SRAM with an Asymmetrical Unit β-ratio Memory Cell”, IEEE International Solid-State Circuits Conference (2008), pp.382, 383, and 622. FIG. 11 illustrates the entire configuration of the semiconductor memory apparatus disclosed by Kawasumi, A. et al. In the example of the circuit illustrated in FIG. 11, a measure is taken to increase the number of dividing a SRAM cell array. That is, the number of SRAM cells controlled by one set of
SRAM control circuits (local read/write circuits) is reduced. In the example of the circuit illustrated in FIG. 11, the number of SRAM cells per bit line pair is reduced to 16, so that the load capacity of the bit line pair is reduced. This reduces the charging time of a bit line at the time of reading. Consequently, this solves not only the issue that the read current and read speed decrease, but also the issue that the memory data can easily be destroyed. The memory data is destroyed at the time of reading by a charge from a bit line pair charged with the power supply voltage VDD flowing into a memory node pair of an SRAM cell that holds low-level. Accordingly, the amount of charge flowing from the bit line pair to the memory node pair decreases by transmitting the memory data quickly to the bit line pair, and thus destruction of memory data can be prevented.
As described so far, in order to improve the read margin of a semiconductor memory apparatus, it is effective to increase the number of dividing an SRAM cell array. In order to improve the read margin without increasing the whole area of a semiconductor memory apparatus, the size of local read/write circuits must be reduced as much as possible. In the circuit of the related art illustrated in FIG. 11, a local read circuit and a local write circuit are made up of 19 transistors in total. It is noted that the local read circuit and the local write circuit are shared by the two SRAM cell arrays, so the number of practical transistors is 9.5, which is a half of all the transistors.
FIG. 12 illustrates a sense amplifier (local read circuit) disclosed in Japanese Unexamined Patent Application Publication No. 6-119784. This sense amplifier and the SRAM cells are connected via a first bit line pair BL and /BL and make up a two-step sense circuit. The sense amplifier disclosed in Japanese Unexamined Patent Application Publication No. 6-119784 does not drive the first bit line pair BL and /BL, so as to increase the read speed and reduce the power consumption.
FIG. 13 is a block diagram of a semiconductor memory apparatus disclosed by Byung-Do Yang et al. in “A Low-Power SRAM Using Hierarchical Bit Line and Local Sense Amplifiers”, IEEE Journal of Solid-State Circuits, vol.40, No. 6, June, 2005, pp.1366 to 1376. The circuit illustrated in FIG. 13 includes a local sense amplifier LSA (local read/write circuits), an access transistor for controlling input/output signals of the local sense amplifier LSA, and multiple SRAM cells. In the circuit disclosed by Byung-Do Yang et al., a word line GWL for controlling the access transistor to be ON/OFF is common to the local sense amplifiers.